Exascale computer architecture adjusting to the “New normal” for computing

Abstract

The current MPI+Fortran ecosystem has sustained HPC application software development for the past decade, but was architected for coarse-grained concurrency largely dominated by bulk-synchronous algorithms. The trends in computer architecture have turned our model for how to get good performance from computing systems upside-down, and will require rethinking our entire programming environment and algorithm design to be better aligned with the new cost metrics for these emerging hardware architectures. There are already promising avenues of exploration underway to mitigate these effects. Future hardware constraints on bandwidth and memory capacity, together with exponential growth in explicit on-chip parallelism will likely require a mass migration to new algorithms and software architecture that is as broad and disruptive as the migration from vector to parallel computing systems that occurred 15 years go. The challenge is to efficiently express massive parallelism and hierarchical data locality without subjecting the programmer to overwhelming complexity. The author covers how changes in hardware (governed by the fundamental physics of Silicon based CMOS technology) are breaking our existing abstract machine models, and DOE's program to overcome these obstacles to continued performance improvements. He examines potential approaches that range from revolutionary asynchronous and dataflow models of computation to evolutionary extensions to existing APIs and OpenMP directives.