Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance

D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy
{"title":"Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance","authors":"D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy","doi":"10.1109/VTSA.2009.5159337","DOIUrl":null,"url":null,"abstract":"We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al<inf>2</inf>O<inf>3</inf>-Si<inf>3</inf>N<inf>4</inf>-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO<inf>2</inf>, HfSiO, Al<inf>2</inf>O<inf>3</inf>, Si<inf>3</inf>N<inf>4</inf>) and tunnel stack sequences (SiO<inf>2</inf>-high-k, SiO<inf>2</inf>-high-k-SiO<inf>2</inf>) are compared. New results are as follows: SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> (OA) BE-TO and SiO<inf>2</inf>/Si<inf>3</inf>N<inf>4</inf>/SiO<inf>2</inf> (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO<inf>2</inf>-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159337","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

Abstract

We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al2O3-Si3N4-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO2, HfSiO, Al2O3, Si3N4) and tunnel stack sequences (SiO2-high-k, SiO2-high-k-SiO2) are compared. New results are as follows: SiO2/Al2O3 (OA) BE-TO and SiO2/Si3N4/SiO2 (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO2-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
带状工程隧道氧化物,用于改进tanos型闪存程序/擦除,具有良好的保留率和100K循环耐久性
我们首次展示了通过带工程隧道氧化物(BETO)改进的电荷阱闪光TaN-Al2O3-Si3N4-“隧道氧化物(TO)”- si mosfet的程序,擦除和耐久性。比较了几种高钾介质(HfO2、HfSiO、Al2O3、Si3N4)和隧道叠层(SiO2-high-k、SiO2-high-k- sio2)。新的结果如下:SiO2/Al2O3 (OA) BE-TO和SiO2/Si3N4/SiO2 (ONO) BE-TO ΔVth窗口比标准SiO2- to提高了300%。OA和ONO堆栈都能承受至少100K的P/E循环,保持窗口值在4V以上。结果与基于高k导价带偏移的模型一致。BE-TO的擦除效率提高,可以在不牺牲P/E窗口的情况下提高耐用性,因为P/E电压应力较低。这些大而持久的窗口有利于多级单元应用,并可能将TANOS闪存扩展到20nm节点以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge? Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity Sub-32nm CMOS technology enhancement for low power applications Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation Inversion-type surface channel In0.53]Ga{in0.47As metal-oxide-semiconductor field-effect transistors with metal-gate/high-k dielectric stack and CMOS-compatible PdGe contacts
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1