AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture

Abstract

AICNN architecture is presented in this work to map the state-of-the-art machine-learning algorithms of CNN to power-constrained embedded hardware. As the combination of analog-to-information conversion and typical CNN algorithms, AICNN can realize ultra-highly efficient computation by using massive parallel analog signal processing circuits, which could also significantly reduce ADC devices cost of converting sensors' outputs. As a design example, the specific AICNN-3 implementation is evaluated, which realize the minimum system of typical CNN task using AICNN architecture, with SMIC 0.18 µm CMOS process. Simulation results show that the AICNN-3 can classify a 28x28 MNIST image with only 1.47nJ. Compared with baseline implementation on CPU, the AICNN-3 could achieve 67000x energy-efficiency improvement, however the accuracy loss is less than 1%. Moreover, the influences of devices mismatch and process variations are evaluated using Monte Carlo statistical method, for the imperfection of analog processing paradigm, as well as the scalability of AICNN architecture is also discussed.