Building reliability into an EPROM cell using in-line WLR monitors

Abstract

A systematic deprogramming failure on a small percentage of the wafers produced on our 0.8 micron EPROM line threatened profitability and reliability. The development of an in-line JEDEC Qbd test on scribe line capacitors lead to the finding of a direct correlation of the inter-poly oxide voltage at breakdown (Vbd) to deprogramming. Using the inline Vbd correlation enabled the discovery of the root cause of deprogramming-asperities growing from the first poly side wall creating a local area of a enhanced field allowing tunneling of electrons from the floating gates during write cycles of adjacent bits. Because the asperities were not created by one source, but from multiple sources, finding the root cause proved to be a formidable task. Before using the in-line Vbd test, wafer sort provided the only feedback. By using the in-line monitor, the evaluation time was reduced by 70%, reducing the time in our cycles of learning. With the reduced cycle time, a systematic approach to finding the root causes became possible. Screening experiments eliminated as many variables as possible. Finally, the contributing process steps were identified and further experiments lead to the development of a robust process. Descriptions of the methods followed and the resulting process changes are discussed.