A 60GHz receiver with 13GHz bandwidth for Gbit/s wireless links in 65nm CMOS

F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A. Mazzanti, F. Svelto
{"title":"A 60GHz receiver with 13GHz bandwidth for Gbit/s wireless links in 65nm CMOS","authors":"F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A. Mazzanti, F. Svelto","doi":"10.1109/ICICDT.2010.5510248","DOIUrl":null,"url":null,"abstract":"This paper presents a wide-band fully integrated receiver for Gbit/s connectivity at mm-waves comprising LNA, RF mixer, quadrature IF mixers, local oscillator (LO), in 65 nm CMOS. The architecture choice is key to meet LO requirements at low power dissipation. We have selected a sliding IF architecture, where the IF frequency, set to 1/3 the RF frequency, slides according to the received frequency. The VCO at 2/3 the RF frequency provides the reference for the first down-conversion and drives two injection locked dividers delivering LO signals for quadrature IF mixing. A Phase Noise of -115 dBc/Hz @ 10 MHz offset from an equivalent 60GHz carrier is achieved with 12.6% frequency tuning range. Coupled interstage resonators are introduced in the low-noise amplifier to extend considerably the gain bandwidth product, leading to more than 13GHz bandwidth with 26dB LNA gain. Selection of the architecture and design of building blocks are discussed in details. Realized prototypes of the receiver show a conversion gain of 35dB, 13GHz RF input bandwidth and noise figure below 6dB with a power dissipation, including LO generation, of 75mW only.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Integrated Circuit Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2010.5510248","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper presents a wide-band fully integrated receiver for Gbit/s connectivity at mm-waves comprising LNA, RF mixer, quadrature IF mixers, local oscillator (LO), in 65 nm CMOS. The architecture choice is key to meet LO requirements at low power dissipation. We have selected a sliding IF architecture, where the IF frequency, set to 1/3 the RF frequency, slides according to the received frequency. The VCO at 2/3 the RF frequency provides the reference for the first down-conversion and drives two injection locked dividers delivering LO signals for quadrature IF mixing. A Phase Noise of -115 dBc/Hz @ 10 MHz offset from an equivalent 60GHz carrier is achieved with 12.6% frequency tuning range. Coupled interstage resonators are introduced in the low-noise amplifier to extend considerably the gain bandwidth product, leading to more than 13GHz bandwidth with 26dB LNA gain. Selection of the architecture and design of building blocks are discussed in details. Realized prototypes of the receiver show a conversion gain of 35dB, 13GHz RF input bandwidth and noise figure below 6dB with a power dissipation, including LO generation, of 75mW only.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
60GHz接收器,13GHz带宽,用于65nm CMOS的Gbit/s无线链路
本文提出了一种基于65nm CMOS的宽带全集成毫米波接收器,包括LNA, RF混频器,正交中频混频器,本振(LO)。在低功耗的情况下,结构的选择是满足LO要求的关键。我们选择了滑动中频架构,其中中频频率设置为射频频率的1/3,根据接收频率滑动。射频频率2/3处的VCO为第一次下变频提供参考,并驱动两个注入锁定分频器,为正交中频混合提供LO信号。在12.6%的频率调谐范围内,从等效60GHz载波获得-115 dBc/Hz @ 10 MHz偏移的相位噪声。在低噪声放大器中引入了耦合级间谐振器,从而大大扩展了增益带宽积,使LNA增益达到26dB,带宽超过13GHz。详细讨论了体系结构的选择和构件的设计。已实现的样机显示,该接收机的转换增益为35dB,射频输入带宽为13GHz,噪声系数低于6dB,功耗(包括LO产生)仅为75mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Improvement of integrated dipole antenna performance using diamond for intra-chip wireless interconnection MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR A new method for performance control of a differential active inductor for low power 2.4GHz applications Power switch optimization and sizing in 65nm PD-SOI considering supply voltage noise Emerging screen technologies impact on application engine IC power
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1