Optimal double-gate MOSFETs: symmetrical or asymmetrical gates?

Abstract

Due to their near-ideal intrinsic features, double-gate (DG) MOSFETs (with thin, fully depleted (FD) Si-film (SOI) bodies) are of interest for possible future CMOS IC applications with L/sub eff/ approaching the lateral scaling limit (/spl sim/20 nm) (Fossum and Chong, 1998; Wong et al. 1998). Much of this interest stems from the two-channel property of the symmetrical-gate DG device and the implied higher current drive. More important, we believe, is the electrical coupling of the two gates through the FD Si film. This coupling underlies the inherent suppression of SCEs and the excellent subthreshold slope, which translate to high I/sub on//I/sub off/ ratios. In fact, as we show in this paper, the coupling can be exploited more in asymmetrical-gate DG MOSFETs (Fossum and Chong, 1998; Tanaka et al. 1994) than in symmetrical ones. We rely on numerical device simulations, using MEDICI and its hydrodynamic-transport option, and SOISPICE circuit simulations, using the UFSOI/FD MOSFET model (Fossum et al. 1998), to convey insight regarding performance and optimal design of DG MOSFETs and to reveal the inherent superiority of asymmetrical gates.