Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors

X. Delord, G. Saucier
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引用次数: 20

Abstract

This paper focuses on the adaptation of a concurrent control-flow checking technique to pipelined RISC microprocessors. This technique, called embedded signature monitoring (ESM), verifies the validity of the instructions executed by the processor. Numerous ESM schemes have been studied with non pipelined processors but up-to-date machines pose new problems. The instruction pipeline of these processors makes difficult to know which instructions are actually executed among the fetched ones: the pipeline may be flushed when a jlowcontrol instruction is executed or when an exception is taken. A behavioural model is presented for the pipeline of most recent processors. It is used to propose a new simple ESM scheme compatible with these processors. This scheme is experienced on the Motorola MC88100 RISC processor. The design of a signature monitor dedicated to this processor is presented and hardware costs are discussed.
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面向流水线RISC微处理器控制流检测的形式化特征分析
本文研究了一种适用于流水线RISC微处理器的并发控制流检测技术。这种技术称为嵌入式签名监视(ESM),用于验证处理器执行的指令的有效性。许多ESM方案已经研究与非流水线处理器,但最新的机器提出了新的问题。这些处理器的指令管道使得很难知道在获取的指令中哪些是实际执行的:当执行jlowcontrol指令或发生异常时,管道可能会刷新。提出了一种针对最新处理器的行为模型。在此基础上提出了一种与这些处理器兼容的简单ESM方案。该方案在摩托罗拉MC88100 RISC处理器上实现。介绍了专用于该处理器的签名监视器的设计,并讨论了硬件成本。
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