Optimization of Gate Oxide of Dual-Gate MISHEMTs for Enhanced DC performance

Abstract

In this paper, simulation study has been carried out to evaluate the impact of high-k gate dielectric on DC performance of Dual-Gate MISHEMTs. Comparison of different gate dielectrics and gate stacks such as $\mathrm {S}\mathrm {i}_{3}\mathrm {N}_{4}, \mathrm {A}1_{2}\mathrm {O}_{3}, \mathrm {H}\mathrm {f}\mathrm {O}_{2}, \mathrm {A}1_{2}\mathrm {O}_{3}/\mathrm {S}\mathrm {i}_{3}\mathrm {N}_{4}, \mathrm {H}\mathrm {f}\mathrm {O}_{2}/\mathrm {S}\mathrm {i}_{3}\mathrm {N}_{4}$ and $\mathrm {H}\mathrm {f}\mathrm {O}_{2}/\mathrm {A}1_{2}\mathrm {O}_{3}$ has been presented. Threshold voltage shift of 10.6% has been observed for $\mathrm {H}\mathrm {f}\mathrm {O}_{2}/\mathrm {A}1_{2}\mathrm {O}_{3}$ gate dielectric stack for DG-MISHEMT if interface charge density were varied from $4.6\times 10^{12}\mathrm {c}\mathrm {m}^{-2}$ to $8\times 10^{12}\mathrm {c}\mathrm {m}^{-2}$ and this shift is minimum as compared to other gate stacks combinations like $\mathrm {A}1_{2}\mathrm {O}_{3}/\mathrm {S}\mathrm {i}_{3}\mathrm {N}_{4}$ or $\mathrm {H}\mathrm {f}\mathrm {O}_{2}/\mathrm {S}\mathrm {i}_{3}\mathrm {N}_{4}$. Also, threshold voltage change is marginal with different stack thickness variation. Simulations were carried out using ATLAS module of SILVACO TCAD tool at ambient temperature.