A 0.5-V, 3-mW, 54/spl times/54-b multiplier with a triple-V/sub th/ CMOS/SIMOX circuit scheme

Abstract

Summary form only given. Sub-1 V CMOS/SOI circuit technology is the most effective candidate for ultra-low-power applications in future ULSIs. We have proposed a triple-V/sub th/ CMOS/SIMOX circuit (Fujii et al., 1998; Douseki et al., 1998) that operates at an ultra low supply voltage of less than 0.5 V. The circuit consists of fully-depleted low- and medium-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power switch transistors. The low-V/sub th/ CMOS logic gates in critical paths and medium-V/sub th/ logic gates in noncritical paths achieve fast operation and leakage current reduction in the active mode. In addition, high-V/sub th/ power-switch transistors dramatically cut the leakage current in the standby mode. To improve circuit performance, the delay time of the critical path in the low-V/sub th/ logic blocks should be reduced and lowand medium-V/sub th/ logic gates should be assigned without any loss of speed. In this paper, we describe a triple-V/sub th/ 54/spl times/54-b multiplier that uses a 108-b adder with a source-controlled transmission-gate multiplexer in the critical path and a Wallace tree block in which low- and medium-V/sub th/ logic gates are automatically assigned using EDA tools.