"Gated-diode" in SOI MOSFETs: a sensitive tool for characterizing the buried Si-SiO/sub 2/ interface

Abstract

Summary form only given. A critical factor in the development of SOI wafers and related CMOS technologies is the quality of the buried Si-SiO/sub 2/ interface. Careful wafer preparation is necessary to obtain reduced surface state density in order to suppress back channel leakage and improve hot carrier reliability and radiation hardness. However, the measurement of the back interface properties and in particular the interface state density remains one of the most difficult parameters to measure in SOI transistors. This is because the large thickness of the buried oxide (relative to gate oxide) renders the usual techniques insensitive and very difficult to apply (Ioannou et al., 1991; Wuters et al., 1989). There has recently been renewed interest in an old technique based on the gated-diode concept (Grove and Fitzelard, 1966), new refinements and modifications of which are being used for the study of current bulk CMOS technologies (Cai and Sah, 1999; Guan et al., 1999). The purpose of this paper is to explain how the presence of two channels makes the adaptation of this technique particularly useful for SOI MOSFETs and suitable for evaluation of the buried interface. The present approach is distinct from and complementary to a recently published modification of the gated-diode technique applied to dual-gate SOI devices for measurement of the recombination lifetime (Ernst et al., 1999).