Yi-Hsuan Chiu, Yi-Bo Liao, M. Chiang, C. Lin, W. Hsu, P. Chiang, Y. Hsu, Wenhsing Liu, S. Sheu, K. Su, M. Kao, M. Tsai
{"title":"Impact of resistance drift on multilevel PCM design","authors":"Yi-Hsuan Chiu, Yi-Bo Liao, M. Chiang, C. Lin, W. Hsu, P. Chiang, Y. Hsu, Wenhsing Liu, S. Sheu, K. Su, M. Kao, M. Tsai","doi":"10.1109/ICICDT.2010.5510298","DOIUrl":null,"url":null,"abstract":"Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Integrated Circuit Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2010.5510298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.
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