Board level flat and vertical drop impact reliability for wafer level chip scale package

Abstract

In this paper, a comprehensive modeling is carried out to investigate the dynamic behaviors of WL-CSP subjected to both flat and vertical drop impacts. The non-linear dynamic properties include solder, Cu pad and the metal stacking under the UBM. Both of the JEDEC standard flat drop test and the vertical drop test modeling for different solder bump height are studied. The results showed that, in the JEDEC standard flat drop test, Stress of the corner balls at each WL-CSP is much higher than the balls in other locations on the same components. The results showed the vertical drop stress is lower than the flat drop stress. The result of JEDEC standard flat drop test modeling showed that the higher solder joint of the WL-CSP can result in lower plastic impact energy but higher tensile (first principal) stress S1 at solder joint.