Cost effective soft error mitigation for parallel adders by exploiting inherent redundancy

Abstract

Soft errors in combinational logic have been considered as an important challenge for VLSI circuit design. As a kind of representative element of combinational logic, adders are widely used in arithmetic units. This paper presents a cost effective soft error mitigation technique for high speed parallel adders. By exploiting inherent hardware redundancy and temporal redundancy of circuit, this technique greatly reduces area overhead and delay overhead of fault tolerance. We also combine C-element-based error correction techniques with inherent hardware and temporal redundancy to enhance error correction capability of adders. In addition, we propose a new metric ADP to evaluate global overheads of soft error mitigation. Experiments show that the proposed technique can correct 93.76% of soft errors only with 12.23% of area and 6.41% of delay overhead. The proposed adder has the least ADP and best tradeoff between area and delay overhead of all previous designs.