R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White
{"title":"An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V","authors":"R. Muralidhar, R. Steimle, M. Sadd, R. Rao, C. Swift, E. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-Min Chang, B. White","doi":"10.1109/ICICDT.2004.1309900","DOIUrl":null,"url":null,"abstract":"This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.