Wafer-level fault isolation approach to debug integrated circuits JTAG failures

Abstract

Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique called frequency mapping can be extended to JTAG data registers shift failures with the help of basic JTAG test methodology knowledge.