A Methodology for Designing Optimal Self-Checking Sequential Circuits

Abstract

This papcl . presents a formal framework for designing self-checking sequen,tial circuits implemented using the monitoriry machine approach. The two main contributions of this paper are: (1) the formulation of the problcm of &;signing an optimal monitoring machine for arbitrcwy fault m,odcls as the problem of minimizi n g an incompletely specified sequential machine, and (2) rlc?iclopin,g a methodology for performing state assignment which results in the monitoring machine hauiruj (L fized number of states for specific fault models. Thx method allows the designer to ezplorc the tradeofl8 between the cost of implementing the main machine and the mon,itoring machine.