Multiple electron beam maskless lithography for high-volume manufacturing

Jack J. H. Chen, S.J. Lin, T. Fang, S. Chang, F. Krečinić, B. Lin
{"title":"Multiple electron beam maskless lithography for high-volume manufacturing","authors":"Jack J. H. Chen, S.J. Lin, T. Fang, S. Chang, F. Krečinić, B. Lin","doi":"10.1109/VTSA.2009.5159308","DOIUrl":null,"url":null,"abstract":"Based on the maturing MEMS capabilities and electronics technologies, the cost effective high-throughput MEBML2, at ≫100 WPH and footprint similar to an optical scanner, can be realized. Resolution, proximity correction, wafer heating and data rate shall not be problems for 5 keV at such high throughput. Another big advantage of focusing on MEBML2 as the lithography solution for 32-nm HP node and beyond is that it only needs investments on developing this tool. Unlike EUV and double patterning, which need enormous investments on the mask infrastructure and process development, besides just the cost of the lithography tool. However, the success of the MEBML2 technology still requires enormous industrial support and investments, which may happen only when it is commonly viewed as one of the mainstream technologies for high-volume manufacturing. To catch up manufacturing of the 32-nm HP node, the clustered platform has to be ready by 2012, which needs big platform suppliers' involvement very soon.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"26 17","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159308","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

Based on the maturing MEMS capabilities and electronics technologies, the cost effective high-throughput MEBML2, at ≫100 WPH and footprint similar to an optical scanner, can be realized. Resolution, proximity correction, wafer heating and data rate shall not be problems for 5 keV at such high throughput. Another big advantage of focusing on MEBML2 as the lithography solution for 32-nm HP node and beyond is that it only needs investments on developing this tool. Unlike EUV and double patterning, which need enormous investments on the mask infrastructure and process development, besides just the cost of the lithography tool. However, the success of the MEBML2 technology still requires enormous industrial support and investments, which may happen only when it is commonly viewed as one of the mainstream technologies for high-volume manufacturing. To catch up manufacturing of the 32-nm HP node, the clustered platform has to be ready by 2012, which needs big platform suppliers' involvement very soon.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于大批量生产的多电子束无掩模光刻技术
基于成熟的MEMS功能和电子技术,可以实现低成本的高通量MEBML2,在< 100 WPH和占地面积类似于光扫描仪。在如此高的吞吐量下,5 keV的分辨率,接近校正,晶圆加热和数据速率应该不是问题。专注于MEBML2作为32nm HP节点及以上光刻解决方案的另一大优势是,它只需要投资开发该工具。不像EUV和双重图案,除了光刻工具的成本之外,还需要在掩模基础设施和工艺开发上进行大量投资。然而,MEBML2技术的成功仍然需要巨大的工业支持和投资,这可能只有当它被普遍视为大批量制造的主流技术之一时才会发生。为了赶上32nm HP节点的生产,集群平台必须在2012年之前准备就绪,这需要大型平台供应商的参与。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge? Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity Sub-32nm CMOS technology enhancement for low power applications Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation Inversion-type surface channel In0.53]Ga{in0.47As metal-oxide-semiconductor field-effect transistors with metal-gate/high-k dielectric stack and CMOS-compatible PdGe contacts
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1