Y. Tsai, David Duartep, N. Vijaykrishnan, M. J. Irwin
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引用次数: 2
Abstract
The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead in 0.25/spl mu/m, 0.18/spl mu/m, 0.07/spl mu/m and 0.065/spl mu/m technologies. HSPICE simulation results and estimations with various function units and memory structures are presented to support a comprehensive analysis.
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