{"title":"Characteristics of submicrometer LOCOS isolation","authors":"J.W. Thomas, J. E. Chung, C. Keast","doi":"10.1109/SOI.1995.526488","DOIUrl":null,"url":null,"abstract":"For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1995.526488","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined.
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