Modeling and optimization of group IV and III–V FinFETs and nano-wires

Abstract

We described simulation methodologies involving a variety of modeling techniques applied to design and optimization of several key aspects of the 7nm and 5nm transistors and standard library cells. Analysis of channel material engineering for the 7nm FinFETs points to different trade-offs for the HP, SP, and LP leakage specs. Mechanical stability of the fins with high aspect ratio is evaluated as a major factor determining fin shape engineering and transitions from bulk FinFET to SOI FinFET and then to NW. Comparative analysis of the 10 track high 2-input NAND library cells based on different channel materials, different spacer materials, and different transistor architectures suggests that the largest benefits of 3.6x speed gain with 5x reduction in power consumption is achieved by switching from 7nm Si baseline FinFET process to 5nm vertical Si NWs. Within lateral transistors at 7nm design rules, transition from fins to lateral NWs and replacing nitride spacers with oxide spacers offer significant speed/power advantage. The channel material engineering brings the weakest advantage on the library cell level.