Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406935

Han Zhou, Xiaoyan Gui, Peng Gao

引用次数: 7

Abstract

A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip (SoC) is proposed in this paper. The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid digital to analog converter (DAC) structure. Scaling capacitor is adopted to improve the precision and reduce the chip area. Through the optimization of placement and routing, the DAC achieves high precision. Besides, a multi-stage comparator is designed, and an offset calibration technique with capacitors is applied, too. The measurement results show that the effective number of bits (ENOB) of this ADC reaches 9.711 bit at Nyquist frequency with 0.83 MHz sampling frequency and the total current of the ADC is 970 μA with a 3.3 V power supply.

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用于IPMI SoC的12位0.83 MS/s SAR ADC的设计

提出了一种内置在片上智能平台管理接口(IPMI)系统中的12位逐次逼近寄存器模拟数字转换器(SAR ADC)。该器件采用中芯国际0.13 μm CMOS工艺，采用全差分C-R混合数模转换器(DAC)结构设计制作。采用缩放电容，提高了精度，减小了芯片面积。通过布局和布线的优化，实现了高精度。此外，还设计了多级比较器，并采用了电容偏置校准技术。测量结果表明，在0.83 MHz采样频率下，该ADC在奈奎斯特频率下的有效位元数(ENOB)达到9.711 bit，在3.3 V电源下，ADC的总电流为970 μA。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 28th IEEE International System-on-Chip Conference (SOCC)

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