Low noise output stage for oversampling audio DAC

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406951

Yujin Park, Han Yang, Hyunjong Kim, Jun Soo Cho, Suhwan Kim

引用次数: 2

Abstract

This paper presents a low noise output stage of oversampling audio digital-to-analog converter (DAC). The proposed glitchless switched capacitor DAC (GSC-DAC) eliminates the penalty of a constrained signal range and a signal distortion caused by return-to-zero signals in SC-DAC that is an essential part in order to convert the digital signal into the analog signal. By using a track and hold circuit and deglitching method in GSC-DAC, the low noise is efficiently achieved. The results of post layout simulation show the noise performance improvements of 21dB on average of SNR, SNDR, SFDR and THD in comparison with the absence of the proposed techniques.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

过采样音频DAC的低噪声输出级

介绍了一种过采样音频数模转换器(DAC)的低噪声输出级。本文提出的无故障开关电容DAC (GSC-DAC)消除了SC-DAC中信号范围受限的缺点和归零信号引起的信号失真，而归零信号是将数字信号转换为模拟信号的重要组成部分。通过在GSC-DAC中采用跟踪保持电路和去毛刺方法，有效地实现了低噪声。布局后仿真结果表明，与未采用上述技术相比，信噪比、SNDR、SFDR和THD的噪声性能平均提高了21dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2015 28th IEEE International System-on-Chip Conference (SOCC)

自引率

0.00%

发文量

期刊最新文献

Per-flow state management technique for high-speed networks A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS Low-latency power-efficient adaptive router design for network-on-chip A multi-level collaboration low-power design based on embedded system A high speed and low power content-addressable memory(CAM) using pipelined scheme