A Wafer-Level 3D Integration Using Bottom-Up Copper Electroplating and Hybrid Metal-Adhesive Bonding

Abstract

We report a wafer-level 3D integration scheme using bottom-up copper electroplating (BCE) and hybrid metal-adhesive wafer bonding. Through-silicon-vias (TSVs) with aspect ratio as high as 13 are plated using BCE without forming voids/seams. Cu-Sn bumps electroplated on the TSVs are used together with polymer adhesive for hybrid bonding. A two-layer 3D integration is achieved using BCE and hybrid bonding, validating the feasibility in fabricating wafer-level 3D integration with high aspect ratio TSVs.