{"title":"CMOS technology roadmap projection including parasitic effects","authors":"Lan Wei, F. Boeuf, T. Skotnicki, H. Wong","doi":"10.1109/VTSA.2009.5159299","DOIUrl":null,"url":null,"abstract":"In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159299","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.
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