450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process

Abstract

A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.