Formal equivalence checking between SLM and RTL descriptions

Abstract

The growing complexity of digital designs makes it harder to discover inconsistency between system level model (SLM) and register transfer level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. Finite State Machines with Data Paths (FSMD) based equivalence checking method is widely used in checking the equivalence between system level and RT level designs. The designs without mapping information can not be handled by many formal methods. Deep state sequences (DSS) based equivalence checking method is one of the state of the art FSMD-based methods that can handle designs without mapping information. DSS is the state sequence from start state to final state of FSMD without repeated paths. It proves the equivalence between SLM and RTL by comparing all the DSS-pairs of FSMDs in SLM and RTL. However the previous proposed DSS-based methods compared all the DSS-pairs blindly, which wasted most verification efforts on useless comparisons. This paper proposes a method to improve the DSS-based equivalence checking method by separating and comparing the corresponding potential equivalent DSS-pairs from all the generated paths to avoid blind comparisons. The promising experimental results show that the proposed method can improve the efficiency of DSS-based equivalence checking method.