Impact of chip package interaction on Cu/Ultra low-k interconnect delamination in Flip Chip Package with large die

Abstract

Die size effects on Chip Package Interaction for Cu/Ultra low-k interconnect in Flip Chip Package were investigated using mechanical and thermal analysis. The analytical and the theoretical study suggested that the die size effects were not caused only by the mismatch in CTE between die and substrate. By considering the number of bonding solder and its mechanical property during the cooling process, the die size dependency of CPI was successfully demonstrated.