Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Chun-Yuan Chen, K. Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, Fu-Liang Yang
{"title":"Vth adjustable self-aligned embedded source/drain Si/Ge nanowire FETs and dopant-free NVMs for 3D sequentially integrated circuit","authors":"Chih-Chao Yang, J. Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, C. Shen, Tsung-Ta Wu, Chun-Yuan Chen, K. Chang-Liao, Jung-Hau Shiu, Meng-Chyi Wu, Fu-Liang Yang","doi":"10.1109/IEDM.2014.7047063","DOIUrl":null,"url":null,"abstract":"3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) V<sub>th</sub> adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for V<sub>th</sub> adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high I<sub>on</sub>/I<sub>off</sub> ratio (>10<sup>5</sup>), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such V<sub>th</sub> adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"3 13","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2014.7047063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
3D stackable high-performance Si nanowire field-effect transistors (NWFETs) and dopant-free Ge junctionless nanowire non-volatile memories (JL-NWNVMs) with self-aligned embedded source/drain (S/D) current boosters and independent back gate (BG) Vth adjusters for 3D sequential integrated circuit are realized by low thermal budget process (<;450°C). The fabricated Si NWFETs exhibit low subthreshold swings (96 and 125 mV/dec.), high on-currents (232 and 110 μA/μm), and large γ value (>0.05) for Vth adjustment. The high-Δ capped blocking dielectric bandgap engineered dopant-free Ge JL-NWNVM exhibits high Ion/Ioff ratio (>105), large memory window (>4V), and low charge loss (<;40%, 10yrs). Thanks to the quantum confinement effect, such Vth adjustable nanowire devices perform well at higher temperatures, which give a wide design window for 3D sequential integrated circuit.