R. Takemura, T. Kawahara, K. Ono, K. Miura, H. Matsuoka, H. Ohno
{"title":"Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond","authors":"R. Takemura, T. Kawahara, K. Ono, K. Miura, H. Matsuoka, H. Ohno","doi":"10.1109/IMW.2010.5488324","DOIUrl":null,"url":null,"abstract":"We propose a disruptive reading and restoring schemes for high-density SPRAM. The proposed scheme uses the feature that, with a desired error rate, TMR device doesn't switch its magnetization of free layer in a specific period of large current pulse. The restoring operation is performed to ensure the storing data. As a result, keeping the good scalability of spin-transfer torque writing toward Gb-scale and beyond, high speed reading with read-disturbance-free operation can be achieved. This operation also enables the SPRAM to accept the DDRx-SDRAM compatible operation.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"52","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2010.5488324","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 52
Abstract
We propose a disruptive reading and restoring schemes for high-density SPRAM. The proposed scheme uses the feature that, with a desired error rate, TMR device doesn't switch its magnetization of free layer in a specific period of large current pulse. The restoring operation is performed to ensure the storing data. As a result, keeping the good scalability of spin-transfer torque writing toward Gb-scale and beyond, high speed reading with read-disturbance-free operation can be achieved. This operation also enables the SPRAM to accept the DDRx-SDRAM compatible operation.