High-speed links for memory interface

Abstract

Memory, as a fundamental component of a system, has been a leading drive for high-speed parallel links, and it requires interface technology providing stable data rate of multi-Gb/s/pin. The highest data rate in memory IO, presented by GDDR5, shows the data rate of up to 6Gb/s/pin with the traditional single-ended signaling on PCB. Further step to higher throughput, however, presents critical problems which must be overcome by taking challenges in packaging, process as well as circuit design. This paper reviews current status of memory interface circuits and introduces several promising interface technologies such as TSV, Wide-IO, inductive coupling, and multiple serial links.