Low-voltage transient bipolar effect induced by dynamic floating-body charging in PD/SOI MOSFETs

M. Pelella, J. Fossum, Dongwoo Suh, S. Krishnan, K. Jenkins
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引用次数: 37

Abstract

Partially-depleted (PD) SOI MOSFETs offer improved threshold control and sensitivity over fully depleted devices, but the effects of dynamic floating-body charging on the threshold voltage VT(t) can possibly lead to instabilities in PD/SOI circuits. We show in this paper that the dynamic charging of the body can also induce a parasitic bipolar-transistor (BJT) transient current which can be significant even at low voltages well below the drain-source breakdown defined by the BJT. Our results indicate that if device/circuit design allows substantial variation of the body charge, then the transient BJT current could be large enough to upset the logic or memory (SRAM or DRAM) function of a chip. They further show that such an upset becomes more probable as the device is scaled, and they give insight regarding device and circuit design to reduce the probability.
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PD/SOI mosfet中动态浮体充电诱导的低压瞬态双极效应
与完全耗尽器件相比,部分耗尽(PD) SOI mosfet提供了更好的阈值控制和灵敏度,但动态浮体充电对阈值电压VT(t)的影响可能导致PD/SOI电路的不稳定。我们在本文中表明,体的动态充电也可以诱导寄生双极晶体管(BJT)瞬态电流,即使在远低于BJT定义的漏源击穿的低电压下,该电流也可以显着。我们的研究结果表明,如果器件/电路设计允许本体电荷的实质性变化,那么瞬态BJT电流可能大到足以扰乱芯片的逻辑或内存(SRAM或DRAM)功能。他们进一步表明,随着设备的缩放,这种混乱变得更有可能,并且他们提供了有关设备和电路设计的见解,以降低概率。
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Analytical threshold voltage model for short channel n/sup +/-p/sup +/ double-gate SOI MOSFETs Front and back gate interface-trap generation due to hot carrier stress in fully depleted SOI/MOSFETs SOI material characterization using optical second harmonic generation Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure Transient effects in floating body SOI NMOSFETs
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