SMAFTI packaging technology for new interconnect hierarchy

Abstract

We have developed a 3-D packaging technology called SMAFTI (SMArt chip connection with FeedThrough Interposer), which enables the implementation of a new memory/logic-interconnect hierarchy. Through experiments, we were able to confirm practical performance of this technology. We implemented a new die bonding process and the multilayer interconnect technology to form over a thousand parallel interconnects between memory and logic dies. Implementation of the new process was achieved with high productivity and low process costs. We characterized the interlaminar horizontal wiring by S-parameter measurement up to 40 GHz and confirmed its potential for high-speed signal transmission at over 10 Gb/s.