L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic

Abstract

The CMOS (Complementary Metal Oxide Semiconductor) technology is the industry standard for chip fabrication. Currently, CMOS faces ever-increasing thermal, power, and miniaturization challenges. As a result, researchers are putting efforts into novel alternative technologies to handle these issues, such as nanomagnetic logic (NML), which uses nanomagnets to perform binary logic. This paper presents a novel L-Shaped clocking scheme to synchronize NML circuits. Our proposal is scalable, simple to use, and reduces the number of constraints for placement and routing algorithms for circuit generation. In addition, the L-Shape clocking scheme introduces tiles with a multi-phase design, which allows for a reduced area overhead at the cost of latency, solves feedback path issues, and introduces a model to work with modern NML features. Our results demonstrate a small latency trade-off for a considerable area reduction. Finally, we validate our work with layouts in Topolinano.