Impact of Gate Oxide Thickness Scaling on Hot-Carrier Degradation in Deep-sub-micron nMOSFETs

Abstract

Infiuence of oxide thickness on hotcarrier investigation criterion are investigated for drain voltages down to 0.85V. In particular we have investigated the dependence of (a) gate bias condition for peak substrate current (b) bias conditions that permit the continued use of lucky electron model for life time prediction and (c) the worst case degradation condition, on the gate oxide thickness. The worst case degradation condition was found to change from V =V /2 to peak substrate current as the oxide thickness was reduced from 5nm to 3nm and also the 3nm oxide showed higher degradation. This change is attributed to the enhanced transverse electric field and the consequent change in the type of the hot-carrier that cause the interface damage from electron to hole.