Realistic fault analysis of CMOS analog building blocks

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595827

P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira

引用次数: 1

Abstract

High quality analog and mixed signal integrated circuits (ICs) require high quality testing. It is shown that test preparation, and test quality improvement of analog building blocks must be layout driven. For this, an IC defects-based analysis is used to study the impact of catastrophic faults on basic CMOS analog blocks. The impact on circuit behavior is analyzed for functional test and for i/sub DD/ power supply fault signatures. It is also demonstrated that a significant part of catastrophic faults cause out of specs performance, and may thus decrease the yield of the product, by an apparent parametric yield degradation. Finally, it is shown that layout level DFT (design for testability) can be rewardingly used to increase test confidence and product quality.

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CMOS模拟模块的实际故障分析

高质量的模拟和混合信号集成电路(ic)需要高质量的测试。结果表明，模拟构件的测试准备和测试质量的提高必须由布局驱动。为此，采用基于集成电路缺陷的分析方法，研究了灾难性故障对基本CMOS模拟模块的影响。分析了功能测试和i/sub DD/电源故障特征对电路行为的影响。研究还表明，很大一部分灾难性故障会导致产品的性能不正常，并可能通过明显的参数良率退化而降低产品的良率。最后，研究表明，布局级DFT(可测试性设计)可以有效地提高测试置信度和产品质量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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