Advanced transistor structures for high performance microprocessors

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI:10.1109/ICICDT.2004.1309909

M. Horstmann, D. Greenlaw, T. Feudel, Andy Wei, K. Frohberg, G. Burbach, M. Gerhardt, Markus Lenski, R. Stephan, K. Wieczorek, Matthias Schaller, J. Hohage, H. Ruelke, J. Klais, P. Huebler, Scott Luning, R. Bentum, G. Grasshoff, C. Schwan, Jon D. Cheek, J. Buller, S. Krishnan, M. Raab, N. Kepler

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引用次数: 2

Abstract

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

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用于高性能微处理器的先进晶体管结构

部分耗尽(PD) SOI技术在生产高速、低功耗微处理器方面已经成熟。本文将重点介绍在开发过程中发现的几个挑战，将40nm栅长(L/sub gate /) PD SOI晶体管引入高速微处理器的量产。为了克服经典栅极氧化物和LGATE缩放，该晶体管开发的关键创新是独特的差分三重间隔结构，在硅沟道中诱导应变的应力层膜和优化的结。这种晶体管结构产生了出色的环形振荡器速度，无负载逆变器延迟为5.5ps。所发现的改进是高度可制造和可扩展的，适用于未来的器件技术，如FD SOI。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)

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