{"title":"Design and implementation of a merged on-line and off-line self-testable architecture","authors":"X. Sun, M. Serra","doi":"10.1109/DFTVS.1993.595817","DOIUrl":null,"url":null,"abstract":"The authors present a new testing scheme which merges concurrent checking and off-line BIST, sharing resources. A simple design template is described, together with an evaluation of area, fault coverage and latency.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1993.595817","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The authors present a new testing scheme which merges concurrent checking and off-line BIST, sharing resources. A simple design template is described, together with an evaluation of area, fault coverage and latency.
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