Sunyeong Lee, J. Jang, J. Shin, H. Kim, H. Bae, D. Yun, D. Kim, D. Kim
{"title":"A novel superlattice band-gap engineered (SBE) capacitorless DRAM cell with extremely short channel length down to 30 nm","authors":"Sunyeong Lee, J. Jang, J. Shin, H. Kim, H. Bae, D. Yun, D. Kim, D. Kim","doi":"10.1109/IMW.2010.5488405","DOIUrl":null,"url":null,"abstract":"We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F<sup>2</sup> (0.0036 µm<sup>2</sup>) feature size. From the 2D TCAD simulation of the SBE capacitorless DRAM cell, thanks to both the Si<inf>0.8</inf>Ge<inf>0.2</inf> quantum well and SiO<inf>2</inf> physical energy barrier, we obtained the sensing margin of 6.4 µA and the retention time of 15 msec.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2010.5488405","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F2 (0.0036 µm2) feature size. From the 2D TCAD simulation of the SBE capacitorless DRAM cell, thanks to both the Si0.8Ge0.2 quantum well and SiO2 physical energy barrier, we obtained the sensing margin of 6.4 µA and the retention time of 15 msec.