ChipPower: an architecture-level leakage simulator

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI:10.1109/SOCC.2004.1362476

Y. Tsai, Ananth Hegde, N. Vijaykrishnan, M. J. Irwin, T. Theocharides

引用次数: 28

Abstract

Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

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ChipPower:一个架构级泄漏模拟器

泄漏功率预计将是未来几代技术的主要挑战之一。温度分布、工艺变化和晶体管数量都对处理器的泄漏功率分布有很大的影响。我们建立了一个模拟器来估计VLIW体系结构的动态/泄漏功率，考虑动态温度反馈和过程变化。该框架基于类似于英特尔安腾IA64的架构，并扩展以模拟其在65纳米技术中实现时的性能。我们的实验结果表明，在65nm技术中，泄漏功率将超过功率预算的50%。此外，如果不包括工艺变化，总泄漏功率将被低估多达30%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International SOC Conference, 2004. Proceedings.

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