A system engineering approach to the design of on-chip electrostatic discharge protection

Abstract

Customer demands for increased ESD protection of CMOS integrated circuit chips and for process enhancements that increase performance but weaken transistors combine to create an important engineering challenge for chip designers. Our objective was to find a common protection solution applicable to the majority of our custom and semicustom chips, using a high profile chip as a design vehicle. This paper describes the development of a technique for quantitative prediction of chip survival (and failure) when stressed according to the Human Body Model. It also describes the development of a design review process to screen weak designs. Careful analyses of successful, unsuccessful and enhanced chip layouts as systems of current paths plus utilization of normal circuit components provide the key ingredients.