Maximum clock frequency distribution model with practical VLSI design considerations

Abstract

A previous model derivation of the maximum clock frequency (FMAX) distribution for a VLSI design is reviewed to enable pre-silicon predictions of frequency bins and process/design optimization for specific product targets. Model projections were compared with measured FMAX data for a 0.25/spl mu/m microprocessor. In this paper, an additional comparison is performed with a 0.13/spl mu/m microprocessor, illustrating the close agreement between the simulated and measured distributions in mean, variance, and shape for different values of temperature and supply voltage. The previous model revealed that within-die variations primarily reduce the mean FMAX, or reciprocally, increase the mean of the maximum critical path delay (T/sub cp,max/) distribution. In this paper, a closed-form analytical equation of the T/sub cp,max/ mean increase is derived as an extension to the FMAX distribution model, which further elucidates the dependency on within-die variations. For a given set of process- and circuit-level parameters, this model provides insight into the delay guard-band required to achieve specific performance goals. Moreover, the model identifies the point of diminishing returns for redesigning critical paths in the tail of the timing histogram. To explore the region of validity, a model assumption for the shape of the critical path delay distribution is examined to guide practical VLSI design decisions.