Novel 3-D structures [ICs]

Abstract

Summary form only given. Interconnect delays are increasingly dominating IC performance due to increased chip size and reductions in minimum feature size. Despite new materials like Cu with low-k dielectrics, interconnect delay is expected to be substantial below the 130 nm technology node, severely limiting chip performance. The need therefore exists for alternative technologies to overcome this problem. One such promising technique is 3D ICs with multiple active Si layers. In a 3D structure, a large number of information signal paths could be transferred from horizontal to vertical interconnects. 3D device integration in multiple Si layers obtainable via technologies like crystallization of amorphous Si and wafer bonding can potentially reduce chip area by increasing transistor packing density and reducing wiring requirements for wire-pitch limited ICs. Recently, we have estimated chip area for 3D ICs and demonstrated significant reductions in interconnect delay for a 0.18 /spl mu/m technology chip with 8 million gates (Souri et al., 1999). In this work, we generalize this analysis using NTRS technology projections down to the 50 nm node. The performance analysis incorporates the effects of increasing the number of active layers, moving repeaters from the substrate to upper active layers and optimizing wiring networks. Interconnect delay as a function of technology is calculated using data projected by the NTRS for 2D ICs. Also shown are delays for 3D ICs with 2 active layers, where wire pitches are increased to match the 2D IC areas, calculated using the 3D chip area estimation model. Interconnect delay is reduced by 64%.