NOR yield enhancement and downstream process variation reduction by STI CMP optimization

Russell McCabe, Suraj KaulKevin Ward, Ronilo Acosta, Bhaskar Pant
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Abstract

Dual STI CMP step recombination was implemented to reduce the variation of the floating gate polysilicon thickness), resulting in less failure from poly foot. Initial qualification of the single oxide CMP showed elevated scratch count, which required DOE modeling with slurry flow rate and tool upgrades to reduce the scratch counts. Once qualified, the recombination showed numerous positive results at probe and post-assembly yield Additional benefits along with the variation reduction was the cycle time improvement along with the cost savings due to merging the dual CMP step into a single step. This change also enabled capacity improvement by qualifying it to run with other technologies and reduced Server SBL(Statistical Bin Limits) breaches driven by poly foot fails.
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STI CMP优化提高NOR良率,减少下游工艺变化
为了减少浮栅多晶硅厚度的变化,采用双STI - CMP阶跃复合,减少了多晶硅的失效。单氧化物CMP的初始鉴定显示划痕数量增加,这需要DOE根据泥浆流速进行建模,并升级工具以减少划痕数量。一旦合格,重组在探针和组装后的产量方面显示出许多积极的结果。除了减少变化之外,还有额外的好处,即由于将双CMP步骤合并为一个步骤,缩短了周期时间,节省了成本。这一更改还使其能够与其他技术一起运行,从而提高了容量,并减少了由多脚故障驱动的服务器SBL(统计Bin限制)漏洞。
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