Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792485
Hoon Kang, Salvin Macwan, Wes Van Erp, Josephine Quek, Bastiaan Saris, Gary R. Huffman, S. Rogers
Supplier management swift strategy development and its deployment, specifically focused on semiconductor commodities parts management will be needed to overcome the unplanned FAB manufacturing facility shutdown. The mechanism development and application on the parts commodities management within procurement organization will be the key enabler for the accelerated unplanned FAB manufacturing facility shutdown recovery. Crisis driving the unplanned FAB shutdown includes natural catastrophic events resulting in power failure, system failure supporting manufacturing facility operations and supply chain crisis. Paper further expands on efficient agile mechanism logic and its application deployed to enable the accelerated recovery of the FAB manufacturing facility in the pre-determined amount of time in order to minimize the revenue impact.
{"title":"Supply crisis parts commodities management during unplanned FAB shutdown recovery","authors":"Hoon Kang, Salvin Macwan, Wes Van Erp, Josephine Quek, Bastiaan Saris, Gary R. Huffman, S. Rogers","doi":"10.1109/asmc54647.2022.9792485","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792485","url":null,"abstract":"Supplier management swift strategy development and its deployment, specifically focused on semiconductor commodities parts management will be needed to overcome the unplanned FAB manufacturing facility shutdown. The mechanism development and application on the parts commodities management within procurement organization will be the key enabler for the accelerated unplanned FAB manufacturing facility shutdown recovery. Crisis driving the unplanned FAB shutdown includes natural catastrophic events resulting in power failure, system failure supporting manufacturing facility operations and supply chain crisis. Paper further expands on efficient agile mechanism logic and its application deployed to enable the accelerated recovery of the FAB manufacturing facility in the pre-determined amount of time in order to minimize the revenue impact.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792492
Liew Siew Wan, Chong Yew Siew
CMP performance is driven by CMP tool, process setting polishing pad, slurry, and diamond disk. The combination effect of input variables on pad material and disk properties were investigated for the process characterization of ILD oxide CMP. The purpose of this study is to evaluate the polishing performance based on ILD CMP used in colloidal silica-based acidic slurry in terms of pad material variation. Polishing key performances are removal rate stability, within wafer non uniformity and defectivity. The goal was to determine a polishing pad which will be able to achieve higher throughput and longer consumable lifetime in ILD CMP process.
{"title":"ILD CMP Polishing Pad and Disk Characterization","authors":"Liew Siew Wan, Chong Yew Siew","doi":"10.1109/asmc54647.2022.9792492","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792492","url":null,"abstract":"CMP performance is driven by CMP tool, process setting polishing pad, slurry, and diamond disk. The combination effect of input variables on pad material and disk properties were investigated for the process characterization of ILD oxide CMP. The purpose of this study is to evaluate the polishing performance based on ILD CMP used in colloidal silica-based acidic slurry in terms of pad material variation. Polishing key performances are removal rate stability, within wafer non uniformity and defectivity. The goal was to determine a polishing pad which will be able to achieve higher throughput and longer consumable lifetime in ILD CMP process.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"54 45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127450422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792475
Jay Zhang, Chee-Hau Ng, S. Kouassi
Glass has unique properties that makes it attractive for certain applications, such as transparency for optical components and low nonlinearity for RF. The Si industry has created highly sophisticated process capabilities in terms of feature size and high precision, among other features. Combining the two creates new possibilities not only in device performance, but also scale economies. This paper discusses challenges in using glass in a Si fab and how to overcome these challenges.
{"title":"Enabling Glass Wafers in a Si Fab","authors":"Jay Zhang, Chee-Hau Ng, S. Kouassi","doi":"10.1109/asmc54647.2022.9792475","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792475","url":null,"abstract":"Glass has unique properties that makes it attractive for certain applications, such as transparency for optical components and low nonlinearity for RF. The Si industry has created highly sophisticated process capabilities in terms of feature size and high precision, among other features. Combining the two creates new possibilities not only in device performance, but also scale economies. This paper discusses challenges in using glass in a Si fab and how to overcome these challenges.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123297441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792487
A. Altun
The paper will introduce a novel 300mm wafer defect review and characterization technology based on universal on-wafer surface-enhanced Raman spectroscopy. The technology can perform high-throughput physical and chemical classification of defects using surface-enhanced optical images and enhanced Raman spectroscopy, respectively. The paper will demonstrate test data regarding size distributions, optical images and Raman spectra of particles of process liquids as well as test wafers.
{"title":"On-wafer organic defect review and classification with universal surface enhanced Raman spectroscopy","authors":"A. Altun","doi":"10.1109/asmc54647.2022.9792487","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792487","url":null,"abstract":"The paper will introduce a novel 300mm wafer defect review and characterization technology based on universal on-wafer surface-enhanced Raman spectroscopy. The technology can perform high-throughput physical and chemical classification of defects using surface-enhanced optical images and enhanced Raman spectroscopy, respectively. The paper will demonstrate test data regarding size distributions, optical images and Raman spectra of particles of process liquids as well as test wafers.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114249644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792479
T. Alcaire, D. Le Cunff, J. Tortai, S. Soulan, V. Brouzet, R. Duru, Christophe Euvrard
Full wafer measurement techniques are used in the semiconductor industry to acquire information at a large scale to control process variation or detect potential defects. This process usually results in the generation of full wafer images, containing various objects that need to be identified to evaluate their impact on the final product performance. Artificial intelligence is very powerful to automate this identification routine. In this paper, we present the application of Region-based Convolutional Neural Networks (RCNN) for enhanced process control from full wafer images gathered by two industrial metrology equipments.
{"title":"Full Wafer Process Control Through Object Detection Using Region-Based Convolutional Neural Networks","authors":"T. Alcaire, D. Le Cunff, J. Tortai, S. Soulan, V. Brouzet, R. Duru, Christophe Euvrard","doi":"10.1109/asmc54647.2022.9792479","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792479","url":null,"abstract":"Full wafer measurement techniques are used in the semiconductor industry to acquire information at a large scale to control process variation or detect potential defects. This process usually results in the generation of full wafer images, containing various objects that need to be identified to evaluate their impact on the final product performance. Artificial intelligence is very powerful to automate this identification routine. In this paper, we present the application of Region-based Convolutional Neural Networks (RCNN) for enhanced process control from full wafer images gathered by two industrial metrology equipments.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129521948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792480
Joshua Roy Palathinkal, Sumit Majumder, Thomas T. Daniel, V. Yadav, R. P. Palathinkal
The fabrication of a sub-10 μm Se-Fe2O3 channel Schottky diode built using cantilever-based Ag-contact printing technology is discussed in this work. There are two phases to the fabrication process. In the first phase, the Ag electrodes are produced using a state-of-the-art micro-girder (μG) cantilever-based in-house printing system. The second phase involves dropcasting the dispersion of leaf-structured Se-Fe2O3 in deionized (DI) water between the printed electrodes. The printed device’s electrical response is observed to be similar to that of a Schottky diode. An analytical model based on the thermionic emission theory was used to verify these features with the acquired experimental results. The ideality factor of the device is extracted as 3.44. At room temperature, the device exhibits a barrier height of 0.72 eV and series resistance of 159 kΩ. As the novel μG printing technology is in its early stages of development, the results presented in this work are preliminary in nature and work on further optimization is being carried out.
{"title":"Fabrication of Se-Fe2O3-based Schottky Diode Using Cantilever-based Ag-contact Printing Technology : Topic: NS/NC - Non-silicon and Non-CMOS","authors":"Joshua Roy Palathinkal, Sumit Majumder, Thomas T. Daniel, V. Yadav, R. P. Palathinkal","doi":"10.1109/asmc54647.2022.9792480","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792480","url":null,"abstract":"The fabrication of a sub-10 μm Se-Fe2O3 channel Schottky diode built using cantilever-based Ag-contact printing technology is discussed in this work. There are two phases to the fabrication process. In the first phase, the Ag electrodes are produced using a state-of-the-art micro-girder (μG) cantilever-based in-house printing system. The second phase involves dropcasting the dispersion of leaf-structured Se-Fe2O3 in deionized (DI) water between the printed electrodes. The printed device’s electrical response is observed to be similar to that of a Schottky diode. An analytical model based on the thermionic emission theory was used to verify these features with the acquired experimental results. The ideality factor of the device is extracted as 3.44. At room temperature, the device exhibits a barrier height of 0.72 eV and series resistance of 159 kΩ. As the novel μG printing technology is in its early stages of development, the results presented in this work are preliminary in nature and work on further optimization is being carried out.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123644555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792529
Yao-An Chung, Yuan-Chieh Chiu, Yu-Fan Chang, Hong-Ji Lee, N. Lian, Tahone Yang, K. Chen, Chih-Yuan Lu
Structural bending of deep slit trench patterns happened in the 3D NAND development. The drawback results in the circuit suffering from missed VIA connections with wordlines (WLs) and common source line (CSL), and unexpectedly high leakage current to impact device operation. Reviewing the images of physical failure analyses (PFA), the slit profile twisting that happened during plasma etching leads to worse line-edge roughness (LER) at the bottom of 12 μm-deep trench. It was also suspected that imbalanced polymer accumulated on the sidewalls of hard mask during etching enhances the electron shielding effect, which makes asymmetrical incident ions trajectory angle worsen the bottom LER. The issues mentioned in this study can be successfully eliminated by etch recipe optimization. The electrical qualification of the slit trench profile requires excellent isolation between bit-lines (BLs) and WLs with less than 1nA of leakage current.
{"title":"Improvement of Twisting and Line-Edge Roughness of 3D NAND Deep Trench Etching on Yield Enhancement : AEPM: Advanced Equipment Processes and Materials","authors":"Yao-An Chung, Yuan-Chieh Chiu, Yu-Fan Chang, Hong-Ji Lee, N. Lian, Tahone Yang, K. Chen, Chih-Yuan Lu","doi":"10.1109/asmc54647.2022.9792529","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792529","url":null,"abstract":"Structural bending of deep slit trench patterns happened in the 3D NAND development. The drawback results in the circuit suffering from missed VIA connections with wordlines (WLs) and common source line (CSL), and unexpectedly high leakage current to impact device operation. Reviewing the images of physical failure analyses (PFA), the slit profile twisting that happened during plasma etching leads to worse line-edge roughness (LER) at the bottom of 12 μm-deep trench. It was also suspected that imbalanced polymer accumulated on the sidewalls of hard mask during etching enhances the electron shielding effect, which makes asymmetrical incident ions trajectory angle worsen the bottom LER. The issues mentioned in this study can be successfully eliminated by etch recipe optimization. The electrical qualification of the slit trench profile requires excellent isolation between bit-lines (BLs) and WLs with less than 1nA of leakage current.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124355137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792476
Namjin Kim, Hojin Choi, J. Chun, Jongpil Jeong
The proposed paper presents an equipment level FDC system for the optimization and anomaly detection of semiconductor equipment. Through the equipment level FDC(Fault Detection and Classification) system, various data in the equipment can be converted into meaningful and accurate analysis data through context mapping to facilitate analysis of the management and condition of the equipment. In addition, it is possible to proactively identify and respond to problems at the equipment level before identifying and responding to problems on the host by processing data of diverse equipment in real time.
提出了一种用于半导体设备优化和异常检测的设备级FDC系统。通过设备级FDC(Fault Detection and Classification，故障检测与分类)系统，可以将设备中的各种数据通过上下文映射转换为有意义、准确的分析数据，便于对设备的管理和状态进行分析。此外，通过实时处理各种设备的数据，可以在主机上发现问题并做出响应之前，在设备层面主动发现问题并做出响应。
{"title":"Introduction of equipment level FDC system for semiconductor wet-cleaning equipment optimization and real-time fault detection","authors":"Namjin Kim, Hojin Choi, J. Chun, Jongpil Jeong","doi":"10.1109/asmc54647.2022.9792476","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792476","url":null,"abstract":"The proposed paper presents an equipment level FDC system for the optimization and anomaly detection of semiconductor equipment. Through the equipment level FDC(Fault Detection and Classification) system, various data in the equipment can be converted into meaningful and accurate analysis data through context mapping to facilitate analysis of the management and condition of the equipment. In addition, it is possible to proactively identify and respond to problems at the equipment level before identifying and responding to problems on the host by processing data of diverse equipment in real time.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"17 S20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132478798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792515
R. van Roijen, Mark Hurley, P. Mirdha, Jeff Brown
At advanced nodes, there is a need for high activation of dopants to achieve the required device performance. At the same time, the high-temperature anneal needed to drive the activation might cause excessive diffusion that conflicts with the tight distribution required for devices with very small dimensions. Laser anneal has been successfully used to meet both requirements. One way to gauge the laser anneal performance is measuring the resistance of a doped silicon test structure. While this is generally very dependable that under certain conditions, we have discovered pattern factor can play a role in the laser anneal process. We show what conditions can cause the deviation and discuss how to evaluate resistance data to ensure a correct interpretation of electrical characteristics.
{"title":"Observation of Pattern Sensitivity In Laser anneal : Topic/category Yield Enhancement","authors":"R. van Roijen, Mark Hurley, P. Mirdha, Jeff Brown","doi":"10.1109/asmc54647.2022.9792515","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792515","url":null,"abstract":"At advanced nodes, there is a need for high activation of dopants to achieve the required device performance. At the same time, the high-temperature anneal needed to drive the activation might cause excessive diffusion that conflicts with the tight distribution required for devices with very small dimensions. Laser anneal has been successfully used to meet both requirements. One way to gauge the laser anneal performance is measuring the resistance of a doped silicon test structure. While this is generally very dependable that under certain conditions, we have discovered pattern factor can play a role in the laser anneal process. We show what conditions can cause the deviation and discuss how to evaluate resistance data to ensure a correct interpretation of electrical characteristics.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131508301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792497
J. Jeong, Dukmin Ahn, Myung-Seon Kim, Eunyoung Han, Youngjeong Kim, Joong Jung Kim
An arcing-like phenomenon taking place around the wafer center area during the wafer spin-cleaning process was investigated. Due to the high-speed rotating operation, friction between materials with very high resistivity such as DI(Deionized) water, dielectric films and non-conductive clean tool hardware builds up surface charge on the wafer. Then it causes arcing or local Si damage by an instantaneous discharge when conductive chemical mixture contact with the surface. In this study, a detailed evolution of the accumulated wafer surface charge was monitored by the real-time electro-static meter, and the disruptive discharging phenomenon was successfully revealed. In order to control the surface charge defects in spin-cleaning process, it was found to be effective to implement an improved cleaning sub-process adding a wafer backside pre-injection step, which safely releases the accumulated surface charge, as well as to adopt a conductive tool chuck and CO2 dissolved water. In addition, it was found through CFD(Computational fluid dynamics) analysis that the charge distribution of the wafer surface is greatly affected by flow characteristics such as the wall shear stress in the DI water rinse process.
{"title":"Identification and Control of Surface Charge Defect Induced by Wafer Spin-Cleaning Process","authors":"J. Jeong, Dukmin Ahn, Myung-Seon Kim, Eunyoung Han, Youngjeong Kim, Joong Jung Kim","doi":"10.1109/asmc54647.2022.9792497","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792497","url":null,"abstract":"An arcing-like phenomenon taking place around the wafer center area during the wafer spin-cleaning process was investigated. Due to the high-speed rotating operation, friction between materials with very high resistivity such as DI(Deionized) water, dielectric films and non-conductive clean tool hardware builds up surface charge on the wafer. Then it causes arcing or local Si damage by an instantaneous discharge when conductive chemical mixture contact with the surface. In this study, a detailed evolution of the accumulated wafer surface charge was monitored by the real-time electro-static meter, and the disruptive discharging phenomenon was successfully revealed. In order to control the surface charge defects in spin-cleaning process, it was found to be effective to implement an improved cleaning sub-process adding a wafer backside pre-injection step, which safely releases the accumulated surface charge, as well as to adopt a conductive tool chuck and CO2 dissolved water. In addition, it was found through CFD(Computational fluid dynamics) analysis that the charge distribution of the wafer surface is greatly affected by flow characteristics such as the wall shear stress in the DI water rinse process.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123179978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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