A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy

Abstract

The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. The authors present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Their model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate their model are discussed.<>