Ensuring robust ESD design with comprehensive reliability verification

Abstract

Weaknesses in electrostatic discharge (ESD) connection paths directly contribute to field failures if they are not properly identified and fixed pre-silicon. Although traditional verification tools such as design rule checking (DRC), layout vs. schematic (LVS) verification and electrical rule checking (ERC) are still required in an integrated circuit (IC) verification flow, they can no longer be the only tools used. This work demonstrates the importance of adding comprehensive reliability checking to the overall IC verification flow to accurately identify reliability issues that cannot be found using traditional verification methods.