Exploration of GFP frame delineation architectures for network processing

Abstract

This paper presents the design and study of circuit architectures for gigabit GFP frame delineation and explores the trade-offs between the data-path (parallelism) and the corresponding hardware cost. The study targets the development of a SoC platform for the design of next generation network processing. Circuits with an 8-bit, 16-bit, 32-bit and a 64-bit data-path have been implemented and analysed in terms of, scalability, hardware cost, speed, and data throughput capabilities. The circuit analysis is based on performance results with the UMC 0.18 /spl mu/m standard cell libraries obtained using Synopsys physical compiler. Analysis shows that the 64-bit datapath architecture is able to achieve data rates beyond l0Gbps whereas the 8-bit data-path architecture is very compact and operates with a clock rate of close to 300MHz. Considering the throughput-rate versus silicon area cost as a measure of silicon area efficiency, then the 16-bit data-path architecture proves to be the most efficient.