Multi-layer SOI island technology by selective epitaxial growth for single-gate and double-gate MOSFETs

Abstract

Continued device scaling in bulk MOSFETs beyond the sub-100 nm regime may require transition to advanced SOI technologies. It has been reported that the thin film fully-depleted (FD) SOI structure is promising for low voltage, high speed applications due to the improved short channel tolerance and lack of body effect (Wong et al, 1998). However, current techniques to obtain bulk-like quality material for very thin SOI have proved difficult to manufacture in terms of cost, material defects and SOI thickness variation across the wafer. The SOI thickness variation results in V/sub T/ variation, which is a major drawback in FD-SOI technology. Selective epitaxial growth (SEG) offers an alternative way of obtaining a device quality SOI material when it is grown laterally (epitaxial lateral overgrowth; ELO) over the field SiO/sub 2/. The local area chemical mechanical polishing (CMP) etch stop gives good controlled thickness of uniform thin SOI films where FD-SOI MOSFETs can be fabricated (Pae et al, 1998 and 1999). One distinctive advantage of the ELO technique is the formation of very thin bottom gate SiO/sub 2/ for double gate MOSFETs (Wong et al. 1997; Denton et al. 1995), which is difficult to obtain in other SOI technologies. This enables improved dynamic V/sub T/ control using low back gate bias. We report here the most recent results of deep-submicron FD-SOI P-MOSFETs fabricated in two different layers of SOI islands created entirely by ELO. Device characteristics and dynamic V/sub T/ shifting are discussed.