The evolutionary spintronic technologies and their usage in high performance computing

Abstract

This paper gives a comprehensive summary of our study in using the spintronic technologies for the on-chip cache density improvement of high performance computing systems. We will start with the spin-transfer torque random access memory (STT-RAM) at the early of stage of commercialization and then extend it to the emerging racetrack memory that has been successfully demonstrated at device and small array level. In multi-level cell (MLC) STT-RAM cache, the cell design constrains, e.g., the switching current requirement and asymmetry in write operations, severely limit the density benefit. Moreover, the two-step read/write accesses and inflexible data mapping strategy may even result in system performance degradation. This paper will discuss our circuit and architecture combined solution. Advanced spintronic technology, i.e., racetrack memory, enables an extremely high storage density and offers a faster-than-Moores law scaling path. Unorthodox new memory hierarchies are necessary to minimize the impact of pseudo-sequential accesses of racetrack memory.