M. Yoshimi, A. Nishiyama, M. Terauchi, O. Arisumi, A. Murakoshi, Y. Ushiku, S. Takeno, K. Suzuki
{"title":"Bandgap engineering technology for suppressing the substrate-floating-effect in 0.15 /spl mu/m SOI-MOSFETs","authors":"M. Yoshimi, A. Nishiyama, M. Terauchi, O. Arisumi, A. Murakoshi, Y. Ushiku, S. Takeno, K. Suzuki","doi":"10.1109/SOI.1995.526470","DOIUrl":null,"url":null,"abstract":"The substrate floating effect is the most fundamental problem in SOI-MOSFETs. Conventional countermeasures, such as body-contact, LDD structure are accompanied by area penalty, Id degradation and other drawbacks. To suppress this effect, we have proposed the bandgap engineering method, in which a narrow bandgap material is formed in the source region. In this paper, an ideal structure for the bandgap engineering is discussed and actually achievable performance is estimated based on simulations and experiments for 0.15 /spl mu/m SOI-MOSFETs.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1995.526470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The substrate floating effect is the most fundamental problem in SOI-MOSFETs. Conventional countermeasures, such as body-contact, LDD structure are accompanied by area penalty, Id degradation and other drawbacks. To suppress this effect, we have proposed the bandgap engineering method, in which a narrow bandgap material is formed in the source region. In this paper, an ideal structure for the bandgap engineering is discussed and actually achievable performance is estimated based on simulations and experiments for 0.15 /spl mu/m SOI-MOSFETs.
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